Method of making miniaturized electronic circuits

ABSTRACT

945,749. Semi-conductor devices. TEXAS INSTRUMENTS Inc. Feb. 2, 1960 [Feb. 6, 1959], No. 32744/63. Divided out of 945,734. Heading H1K. The subject matter of this Specification is included in Specification 945,734 from which the present Specification is divided but the claims relate to a device comprising a semi-conductor body with three superposed regions of alternate conductivity types forming a pair of PN junctions extending to a surface of the body and there defining two enclosed areas one within the other, with an insulating oxide of a semi-conductor covering selected parts of said surface, first and second ohmic contacts secured to said surface on opposite sides of the inner PN junction and a third ohmic contact secured to the third region. Specifications 945,737, 945,738, 945,739, 945,740, 945,741, 945,742, 945,743, 945,744, 945,745, 945,746, 945,747 and 945,748 also are referred to.

July 19, 1966 J. S. KILBY METHOD OF MAKING MINIATURIZED ELECTRONIC CIRCUITS Original Filed Feb. 6, 1959 4 Sheets-Sheet 1 INVENTOR Jack 6, Kb'iby BY \gaw w. 71%

ATTORNEY J. S. KlLBY July 19, 1966 METHOD OF MAKING MINIATURIZED ELECTRONIC CIRCUITS 4 Sheets-Sheet 2 Original Filed Feb. 6. 1959 NA 33 Q Q Qn MUSRSQ Lats M SQQQ \T LESQ Nibg INVENTOR Jack a. Kzlby ATTORNEY July 19, 1966 J. s. KILBY 3,261,081

METHOD OF MAKING MINIATURIZED ELECTRONIC CIRCUITS Original Filed Feb. 6, 1959 4 Sheets-Sheet 5 INVENTOR Jack S K6553 ATTORNEY J. S. KILBY July 19, 1966 METHOD OF MAKING MINIATURIZED ELECTRONIC CIRCUITS 4 Sheets-Sheet 4 Original Filed Feb. 6. 1959 INVENTOR Jack a, ma

kbqkbb ATTORNEY United States Patent 3,261,081 METHOD OF MAKING MINIATURIZED ELECTRONIC CIRCUITS Jack S. Kilby, Dallas, Tex., assignor to Texas Instruments Incorporated, Dallas Tex., a corporation of Delaware Original application Feb. 6, 1959, Ser. No. 791,602, now Patent No. 3,138,743, dated June 23, 1964. Divided and this application Mar. 16, 1964, Ser. No. 352,380 21 Claims. (Cl. 29155.5)

This is a divisional application of my copending application Serial No. 791,602, filed Feb. 6, 1959, now Patent No. 3,138,743, issued June 23, 1964.

This invention relates to methods for fabricating miniaturized electronic circuits. More particularly, this invention relates to fabrication of integrated electronic circuits from semiconductor material.

Many methods and techniques for min-iaturizing electronic circuits have been proposed in the past. At first, most of the effort Was spent upon reducing the size of the components and packing them more closely together. Work directed toward reducing component size is still going on but has nearly reached a limit. Other efforts have been made to reduce the size of electronic circuits such as by eliminating the protective coverings from components, by using more or less conventional techniques to form components on a single substrate, and by providing the components with a uniform size and shape to permit closer spacings in the circuit packaging therefor.

All of these methods and techniques require a very large number and variety of operations in fabricating a complete circuit. For example, of all circuit components, resistors are usually considered the most simple to form, but when adapted for miniaturization by conventional techniques, fabrication requires at least the following steps:

(a) Formation of the substrate.

(b) Preparation of the substrate.

(0) Application of terminations.

((1) Preparation of resistor material.

(e) Application of the resistor material.

(f) Heat treatment of the resistor material. (g) Protection or stabilization of the resistor.

Capacitors, transistors, and diodes when adapted for miniaturization each require at least as many steps in the fabrication thereof. Unfortunately, many of the steps required are not compatible. A treatment that is desirable for the protection of a resistor may damage another element, such as a capacitor or transistor, and as the size of the complete circuit is reduced, such conflicting treatments, or interactions, become of increasing importance. Interactions may be minimized by forming the components separately and then assembling them into a complete package, but the very act of assembly may cause damage to the more sensitive components.

Because of the large number of operations required, control over miniaturized circuit fabrication becomes very difficult. To illustrate, many raw materials must be evaluated and controlled even though they may not be well understood. Further, many testing operations are required and, even though a high yield may be obtained for each operation, so many operations are re quired that the over-all yield is often quite low. In service, the reliability of a circuit produced by methods of such complexity may also be quite low due to the tremendous number of controls required. Additionally, the separate formation of individual components requires individual terminations for each component. These terminations may eventually become as small as a dot of conductive paint. However, they still account for a large fraction of the usable area or volume of the circuit and may become an additional cause of circuit failure or rejection due to misalignment.

In contrast to the approaches to miniaturization that have been made in the past, the present invention has resulted from a new and totally different concept for miniaturization. Radically departing from the teachings of the art, it is proposed by the invention that miniaturization can best be attained by use of as few materials and operations as possible. In accordance with the principles of the invention, the ultimate in circuit miniaturization is attained using only one material for all circuit elements and a limited number of compatible process steps for the production thereof.

The above is accomplished by the present invention by utilizing a body of semiconductor material exhibiting one type of conductivity, either n-type or p-type, and having formed therein a diffused region or regions of appropriate conductivity type to form a p-n junction between such region or regions and the semiconductor body or, as the case may be, between diffused regions. According to the principles of this invention, all components of an entire electronic circuit are fabricated within the body so characterized by adapting the novel techniques to be described in detail hereinafter. It is to be noted that all components of the circuit are integrated into the body of semiconductor material and constitute portions thereof.

In a more specific conception of the invention, all components of an electronic circuit are formed in or near one surface of a relatively thin semiconductor wafer characterized by a diffused p-n junction or junctions. Of importance to this invention is the concept of shaping. This shaping concept makes it possible in a circuit to obtain the necessary isolation between components and to define the components or, stated differently, to limit the area which is utilized for a given component. Shaping may be accomplished in a given circuit in one or more of several different ways. These various ways include actual removal of portions of the semiconductor material, specialized configurations of the semiconductor material such as long and narrow, L-shaped, U-shaped, etc., selective conversion of intrinsic semiconductor material by diffusion of impurities therein to to provide low resistivity paths for current flow, and selective conversion of semiconductor material of one conductivity type to conductivity of the opposite type wherein the p-n junction there by formed acts as a barrier to current flow. In any event, the effect of shaping is to direct and/or confine paths for current flow thus permitting the fabrication of circuits which could not otherwise be obtained in a single wafer of semiconductor material. As a result, the final circuit is arranged in essentially planar form. It is possible to shape the wafer during processing and to produce by diffusion the various circuit elements in a desired and proper relationship. Certain of the resistor and capacitor components described herein have utility and novelty in and of themselves although they are completely adaptable to and perhaps find their greatest utility as integral parts of the semiconductor electronic circuit hereof.

It is, therefore, a principal object of this invention to provide a novel miniaturized electronic circuit fabricated from a body of semiconductor material containing a diffused p-n junction wherein all components of the electronic circuit are completely integrated into the body of semiconductor material.

It is another principal object of this invention to produce desired circuits by appropriately shaping a wafer of semiconductor material to obtain the necessary isolation between components thereof and to define the areas utilized by such components.

It is a further object of this invention to provide a unique miniaturized electronic circuit fabricated as described whereby the resulting electronic circuit will be substantially smaller, more compact, and simpler than circuit packages heretofore developed using known techrnques.

It is a still further object of this invention to provide novel miniaturized electronic circuits fabricated as described above which involve less processing than techniques heretofore used for this purpose.

It is another object of this invention to provide novel resistor and capacitor circuit components.

Other and further objects of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention when taken in conjunction with the appended drawings, in which:

FIGURES I-Sa illustrate schematically various circuit components fabricated in accordance with the principles of the present invention in order that they may be integrated into, or as they constitute parts of, a single body of semiconductor material;

FIGURE 6a illustrates schematically a multivibrator circuit fabricated in accordance with the present invention;

FIGURE 6b shows the wiring diagram for the multivibrator circuit of FIGURE 6a laid out in the same relationship;

FIGURE 7 illustrates the wiring diagram of the multivibrator circuit of FIGURE 6a in a more conventional presentation;

FIGURE 8a illustrates schematically a phase shift oscillator fabricated in accordance with the principles of the present invention;

FIGURE 8b shows the wiring diagram for FIGURE 8a with the components laid out in the same relationship; and

FIGURE 8c portrays the wiring diagram of the phase shift oscillator.

Referring now to the drawings in detail, preferred embodiments of the present invention will now be described in detail in order that a better understanding of the principles of the invention and the various forms and embodiments of the invention will be better understood.

As noted previously, the invention is primarily concerned with miniaturization of electronic circuits. Also, as noted, the invention contemplates the use of a body of semiconductor material appropriately shaped and having formed therein a diffused p-n junction or junctions and the use of component designs for the various circuit elements or components which can .be integrated into or which constitute parts of the aforesaid body of semiconductor material.

FIGURES 1-5 inclusive illustrate in detail circuit elements designed in accordance with the principles of this invention which can be integrated into a body of semiconductor material. It is noted at this point that the body of semiconductor material is of single crystal structure, and can be composed of any suitable semiconductor material. There may be mentioned as examples of suitable materials germanium, silicon, intermetallic alloys such as gallium arsenide, aluminum antimonide, indium antimonide, as well as others.

Referring particularly to FIGURE 1, there is shown a typical design for a resistor which may be embodied or integrated into a body of single crystal semiconductor material. As noted in FIGURE 1, the design contemplates utilizing the bulk resistance of a body 10 of semiconductor material of either nor p-type conductivity. Contacts 11 and 12 are made ohmically to one surface of the body 10, spaced apart a sufficient distance to achieve a desired resistance. If two resistors are to be connected together, it is not necessary to provide separate terminations for the common point. The resistance may be calculated from where L is the active length in centimeters, A is the cross sectional area, and p is the resistivity in ohm-cm. of the semiconductor material.

In addition to the resistor shown in FIGURE 1, a resistor may be provided as shown in FIGURE la for integration into and as forming a part of a body of semiconductor material. In FIGURE la, there is shown a body of p-type semiconductor material with an n-type region 10!) formed therein. Of course, between the body 10:: and region 1012 there is a p-n junction which is designated by the numeral 13. Contacts 11a and are made to one surface of the region 1%, spaced apart from each other in order to achieve a desired resistance. As in FIGURE 1, the contacts 11a and 12a are ohmic contacts to the region 1011. A resistor formed in the manner of FIGURE la has several important advantages. First, the p-n junction 13 provides a barrier to current flow from the n-type region 1% into the p-type body 10a and, thus, the current flow is confined to a path in the n-type region 10b between the contacts thereto. The second advantage is that the total resistance value thereof can be controlled to a large degree. The total resistance value may be controlled by etching very lightly over the entire surface to remove the uppermost portion of the n-type region 1%, being very careful to not etch through the p-n junction, and as well by selectively etching to or through the p-n junction 13 thereby effectively to increase the length of the path traveled by the current between the contacts. The third, and perhaps major, advantage in forming a resistor according to FIGURE 1a is in that, by controlling the doping level or impurity concentration in the n-type region 10b, lower and more nearly constant temperature coeflicients may be provided for the resistor. The above description has been in terms of a p-type body 100 and an n-type region 10b but it is obvious that the body 1011 could be equally as well of n-type conductivity and the region 10b of p-type conductivity. The resistors of FIG- URE 1a may be formed as separate circuit elements or components.

Capacitor designs may he obtained by utilizing the capacitance of a p-n junction, as shown in FIGURE 2, wherein a semiconductor wafer 15 of p-type conductivity is shown containing an n-type diffused layer 16. Ohmic contacts 17 are made to opposite faces of the wafer 15. The capacitance of the diffused junction is given by where A is the area of the junction in square cm., 6 is the dielectric constant, q is electronic charge, and V is the applied voltage.

Instead of the capacitor of FIGURE 2, capacitance in a body of single crystal of semiconductor material may be provided as shown and descdibed in connection with FIGURE 2a. FIGURE 2a shows a body 15:: of semiconductor material, of either nor p-type conductivity, which constitutes one plate of the capacitor. Evaporated onto the body 15a is a layer 18 providing a dielectric layer for the capacitor. It is necessary that the layer 18 have a suitable dielectric constant and be inert when in contact with the semiconductor body 15a. Silicon oxide has been found to be a suitable material for dielectric layer 18 and may be applied by evaporation or thermal oxidation techniques onto body 15a. Plate 19 forms the other plate of the capacitor and is provided by evaporating a conductive material onto layer 18. Gold and aluminum have been found to be satisfactory materials for the plate 19. Ohmic contact 17a is made to the body of semiconductor material 15a and contact to plate 19 may be made by any suitable electrical contact (not shown). Capacitors formed in the manner described in connection with FIGURE 2a have been found to provide much more stable capacitors than pure junction capacitors, that is, p-n junction capacitors, and, of course, may be fabricated as separate elements or components.

Capacitors produced in the manner of FIGURE 2 are also diodes, and must therefore be properly polarized in the circuit. Non-polar capacitors may be made by connecting two such areas back-to-back. Although junction capacitors have a marked voltage dependence, such dependence is present to a lesser degree for low voltages in then non-polar configuration.

Resistor and capacitor designs may be combined to form a distributed R-C network. Such is shown in FIG- URE 3, wherein a wafer 20 of p-type conductivity having an n-type conductivity diffused layer 21 formed therein is provided with a broad area contact 22 on the face and spaced contacts 23 on the opposite face. These networks are useful for low pass-filters, phase shift networks, coupling elements, etc. Their parameters may be calculated from the equations above. Other configurations of this general type are also possible.

Transistors and diodes may be formed on a wafer, as described by Lee in Bell System Technical Journal, vol. 35, p. 23 (1956). This reference describes a transistor, as shown in FIGURE 4, which has a collector region 25, a diffused p-n junction 26, a base layer 27, an emitter contact 28 forming .a rectifying connection with base layer 27 and base and collector contacts 29 and 30, respectively. The base layer 27 is formed as a mesa of small cross section. A diode of similar design is shown in FIGURE 5, and consists of a region 35 of one type conductivity, a mesa region 36 of opposite conductivity type with a p-n diffused junction formed therebetween and contacts 37 and 38 to each region.

Small inductances, suitable for high frequency use, may also be made by shaping the semiconductor as evidenced by FIGURE 5a which shows a spiral of semiconductor material. It is also possible to prepare photosensitive, photoresistive, solar cells and other like com ponents utilizing the basic design considerations outlined above.

Although all of the circuit elements have been described in terms of a single diffused layer, it is quite possible to use a double diffused structure. Double diffusion may thus provide both n-p-n or p-n-p structures. Also, any suitable materials can be employed for the semiconductor materials, conductivity producing impurities, and contact materials. Also, suitable and known processing can be used to produce the above circuit designs.

Because all of the circuit designs described above can be formed from a single material, a semiconductor, it is possible by shaping to integrate all of them into a single crystal semiconductor wafer containing a diff-used p-njunction, or junctions, and to process the wafer to provide the proper circuit and the correct component values. Junction areas for the transistors, diodes, and capacitors are formed by properly shaped mesas on the wafer.

A specific illustration of an electronic circuit embodying the principles of the invention is shown in FIGURE 60!. As shown, a thin wafer of single crystal semiconductor material containing a diffused p-n junction has been processed and shaped to include a complete and integrated multivibrator electronic circuit formed essentially in one surface of the wafer. The regions of the wafer have been marked with symbols representative of the circuit element functions that are performed in the various regions. FIGURE 6b shows a wiring diagram of the various circuit functions in the relationship which they occupy in the wafer of FIGURE 6a. A more conventionally drawn circuit diagram is shown in FIGURE 7 with the circuit values actually used. The multivibrator circuit shown in FIGURES 6a, 6b and 7 will be described as illustrative of the processing techniques required. First, a semiconducting wafer, preferably silicon or germanium, of the proper resistivity is lapped and polished on one side. For this design, 3 ohm-cm. p-type germanium was used. The wafer was then subjected to an antimony diffusion process which produced an n-type layer on the surface about 0.7 mil deep. The wafer was then cut to the proper size, 0.200 0.080 and the unpolished surface was lapped to give a wafer thickness of 0.0025 inch.

Gold plated Kovar leads '50 were attached by alloying to the wafer in the proper positions. Kovar is a trade name for an iron-nickel-cobalt alloy. Gold was then evaporated through a mask to provide the areas 5154 which provide ohmic contact with the n region, such as the transistor base connections and the capacitor contacts. Aluminum was evaporated through a properly shaped mask to provide the transistor emitter areas 56, which form rectifying contacts with the n layer.

The wafer was then coated with a photosensitive resist or lacquer, such as Eastman Photo Resist, supplied by Eastman Kodak Company, and exposed through a negative to a light. The lacquer image remaining after development was used as a resist for etching the wafer to the proper shape. In particular, this etching forms a slot through the wafer to provide isolation between R and R and the rest of the circuit, and also shapes all of the resistor areas to the previously calculated configuration. Either chemical etching or electrolytic etching may be used, although electrolytic etching appears to be preferable.

After this step, the photoresist was removed with a solvent, and the mesa areas 60 masked by the same photographic process. The wafer was again immersed in etchant, and the n layer completely removed in the exposed areas. A chemical etch is considered preferable. The photoresist was then removed.

Gold wires 70 were then thermally bonded to the appropriate areas to complete the connections, and a final clean-up etch given. Instead of using the gold wires '70 in making electrical connections, connections may be provide-d in other ways. For example, an insulating and inert material such as silicon oxide may be evaporated onto the semiconductor circuit wafer through a mask either to cover the wafer completely except at the points where electrical contact is to be made thereto, or to cover only selected portions joining the points to be electrically connected. Electrically conducting material such as gold may then be laid down on the insulating material to make the necessary electrical circuit connections.

After testing, the circuit may be hermetically sealed, if required, for protection against contamination. The finished device 'was smaller by several orders of magnitude than any others which have previously been proposed. Because the fabrication steps required are quite similar to those now used in manufacturing transistors, and because of the relatively small number of steps required, these devices are inherently inexpensive and reliable, as well as compact.

A further illustration of the process hereof is shown in FIGURES 8a-8c. Each area of the single crystal semiconductor wafer has been marked with a symbol for the circuit element which it represents. This unit illustrates the use of resistors, transistors, and a distributed R-C network to form a complete phase shift oscillator.

It must be emphasized that the two embodiments described above are merely two of innumerable circuits which can be fabricated by the techniques of the present invention. There is no limit upon the complexity or configuration of circuits which can be made in this manner. While there is a limit upon the types and values of components which can be made in a limited space, the invention hereof nevertheless represents a remarkable improvement over the prior art. As evidence of the advance in the art accomplished by the present invention, it is possible using the techniques described above to achieve component densities of greater than thirty million per cubic foot as compared with five hundred thousand per cubic foot which is the highest component densities attained prior to this invention.

Although the invention has been shown and described in terms of specific embodiments, it will be evident that changes and modifications are possible which do not in fact depart from the inventive concepts taught herein. Hence, such changes and modifications are deemed to fall within the purview of the invention.

What is claimed is:

1. In a method of manufacturing an integrated circuit of the type having a plurality of separate transistors and a plurality of separate passive circuit components including elongated semiconductor resistors in a semiconductor body, the steps of diffusing conductivity-determining impurity material into one face of the body to convert the conductivity-type of semiconductor material adjacent said one face to form what in the completed integrated circuit functions as the base regions of said plurality of transistors and to form at the same time what in the completed integrated circuit functions as at least parts of said passive circuit components, applying contacts to a face of the body at opposite ends of said elongated semiconductor resistors, and applying interconnections to connect selected ones of the passive circuit components including said semiconductor resistors to selected ones of the transsistors, the method including the steps of treating the body to electrically isolate said base regions from one another and from said parts of the passive circuit components.

2. The method of fabricating an integrated circuit comprising the steps of: diffusing conductivity-determining impurities into a first area of a semiconductor body adjacent a major face of said body to form a region of an active circuit element, While simultaneously therewith diffusing conductivity-determinin g impurities into another area of the body adjacent to said one major face but spaced on said one face from said first area to form a region which provides at least a part of a passive circuit element, and applying electrical connecting means on said one face to provide in the completed device an integrated electronic circuit which includes said active and passive circuit elements, said method including the step of processing the body to provide substantial electrical impedance between said areas whereby substantial electrical isolation is obtained.

3. A method of fabricating an integrated circuit comprising introducing into the surface of a major face of a body of semiconductor material conductivity-determining impurities at spaced apart locations on said one face to form simultaneously like regions of a plurality of junction transistors and like regions of a plurality of passive electronic circuit elements, and securing to said major face a plurality of electrically conductive means external to the semiconductor material to interconnect selected ones of the transistors and selected ones of the passive circuit elements, said method including the step of processing the body to provide substantial electrical isolation between said spaced apart locations.

4. A method of fabricating an integrated circuit as in claim 3 wherein said processing includes shaping by physical removal of at least some of the semiconductor material of the body.

5. A method according to claim 4 wherein unwanted semiconductor material is completely removed through the body from one major face to the opposite major face.

6. In a method of manufacturing an integrated circuit device of the type having a plurality of separate active circuit components and a plurality of separate passive circuit components in a semiconductor body, the steps of providing a wafer of extrinsic semiconductor material, diffusing into one face of the body conductivitydetermining impurity material to form surface-adjacent areas which in the completed device provide separate like regions of the active circuit components and to form at the same time areas Which in the completed device provide separate like regions of the passive circuit components, and applying contacts and interconnections to said one face of the wafer to connect selected ones of said regions of the passive circuit components to selected ones of the active circuit components, said method including the step of treating said one face of the wafer to provide electrical isolation between said regions of the active circuit components and said regions of the passive circuit components.

7. In a method according to claim 6, said step of treating said one face of the wafer to provide electrical isolation between said regions of the active circuit components and said regions of the passive circuit components including removing semiconductor material of the wafer from one major face to the opposite major face.

8. In a method according to claim 6, said step of treating comprising removing selected portions of said one face of the wafer after said step of diffusing to leave raised mesas on said one face.

9. In a method of manufacturing an integrated circuit of the type having a plurality of separate active circuit components and a plurality of separate passive circuit components including elongated semiconductor resistors in a semiconductor body, the steps of diffusing conductivity-determining impurity material into one face of the body to convert the conductivity-type of semiconductor material adjacent said one face to form what in the completed integrated circuit functions as separate regions of said plurality of active circuit components and to form at the same time what in the completed integrated circuit functions as at least parts of said passive circuit components, and applying contacts to a face of the wafer at opposite ends of said elongated semiconductor resistors and to selected portions of said active circuit components at said one face and applying interconnections to connect selected ones of the passive circuit components including said semiconductor resistors to selected ones of the active circuit components, said method including the step of processing the body to provide electrical isolation between the active and passive circuit components.

10. In a method of fabricating a semiconductor device of the type having at least one active circuit element and at least one passive circuit element in a Wafer of semiconductor material adjacent a major face thereof, the steps of forming in the wafer one region of said active circuit element, with such region being of conductivitytype opposite to subjacent semiconductor material, by introducing conductivity-type determining material into said region, forming in the wafer at a position spaced on said one face from the active circuit element an elongated surface-adjacent region Which is at least part of said passive circuit element, with the region being of conductivity-type opposite to subjacent semiconductor material, by introducing conductivity-type determining material into said elongated region, and securing electrical connecting means to said one face of the wafer, external of the wafer, to interconnect said active circuit element with said passive circuit element, said method including the step of treating the wafer to obtain isolation through the wafer between wafer portions which in the completed device form said active and passive circuit elements.

11. A method of producing miniaturized electronic circuits comprising the steps of:

(a) obtaining a wafer of single crystal semiconductor material of one conductivity type,

(b) diffusing desired amounts of conductivity type determining impurities into said wafer to create therein an active component and a passive component,

(c) shaping said wafer to obtain isolation between said components and to define the areas utilized by said components in said wafer,

(d) and providing electrical connections to complete the circuit.

12. The method of fabricating a solid state circuit device having at least one active element and one passive element comprising the steps of:

(a) forming a Wafer of semiconductor material doped with one type conductivity-producing ingredient,

(b) forming in one part of said wafer a portion predominantly doped with an opposite type conductivityproducing ingredient to produce [a transistor region selected from the class of emitter, base and collector,

(c) concurrently forming in another part of said wafer a portion predominantly doped with said opposite type conductivity-producing ingredient to produce one region of said passive element,

(d) andsecuring to the wafer electrically conductive means to connect said elements into an electronic circuit,

said method including the step of treating the wafer to provide electrical isolation between said active and passive elements.

13. The method of fabricating a solid state circuit device having at least one active element and one passive element comprising the steps of:

(a) forming in a wafer of doped semiconductor material one transistor region selected from the regions of emitter, base and collector,

(b) while concurrently forming in said wafer a region of saidpassive element,

(c) and securing to the Wafer electrically conductive means to connect the active and passive elements into an electric circuit,

said methodincluding the step of processing the wafer to obtain electrical separation through the wafer between wafer portions which in the completed device form said active and passive circuit elements.

14. The method of fabricating a solid state circuit device having'at least one active element and one passive element comprising the steps of:

(a) forming a wafer of semiconductor material doped with one type coductivity-producing ingredient,

(b) diffusing into one area of said wafer an opposite type conductivity-producing ingredient to form a transistor region selected from the class of emitter, base and collector,

() while concurrently difiusing an ingredient of said opposite. type conductivity into another separate region of said wafer to form one region of said passive element,

(d) and applying to the wafer electrically conductive means to connect the active and passive elements into an electronic circuit,

said method including the step of treating the wafer to provide electrical isolation between active and passive circuit elements.

15. The method of fabricating a solid state circuit device having at least one active element and one passive element comprising the steps of:

(a) masking a wafer of doped semiconductor material with masking means to expose preselected areas of said wafer,

(b) and diifusing through said masking means a selected conductivity-type ingredient to form at least a part of one of said elements,

(c) applying to the wafer electrically conductive means to connect the active and passive elements into an electronic circuit,

said method including the step of treating the wafer to provide electrical separation between the active and passive elements.

16. The method of fabricating a solid state embodiment of an entire electronic circuit having at least one transistor, one resistor, and one capacitor, comprising the steps of:

(a) forming a doped wafer of semiconductor material,

(b) introducing an ingredient of opposite type conductivity into at least a part of said wafer to form one region of said transistor and at least a part of one of said resistor and capacitor,

(c) introducing at least one additional conductivityproducing ingredient in said wafer to form an additional portion of said transistor,

(d) and applying to the wafer electrically conductive means to connect the transistor, resistor and capacitor in an electronic circuit,

said method including the step of treating the wafer to provide electrical isolation between the transistor and the resistor and capacitor.

17. The method of fabricating a solid state embodiment of a complete electronic circuit comprising at least one transistor, a resistor, and a capacitor comprising the steps of:

(a) forming a wafer of doped semiconductor material, (b) introducing into at least one region of said wafer an impurity ingredient of opposite conductivity type to form concurrently at least one portion of each of said transistor, resistor, and capacitor,

(c) securing to the wafer electrically conductive means to connect the transistor, resistor and capacitor in an electronic circuit,

said method including the step of treating the wafer to obtain electrical separation between the transistor and the resistor and capacitor.

18. The method of fabricating a solid state circuit device having a diode and an inductor comprising the steps of:

(a) introducing into one part of a doped semiconductor wafer an ingredient to form one region of said diode,

(b) introducing into another part of said doped semiconductor Wafer an ingredient to form one region of said inductor,

(c) and applying to the wafer electrically conductive means to connect said diode and inductor in an electronic circuit,

said method including the step of treating the wafer to provide electrical isolation between the diode and the inductor.

19. The method of fabricating a solid state circuit device having a diode and an inductor comprising the steps of:

(a) introducing into one part of a doped semiconductor wafer an ingredient to form one region of said diode,

(b) shaping another part of said Wafer to form one region of said inductor,

(c) and applying to the wafer electrically conductive means to connect said diode and inductor in an electronic circuit.

20. The method of fabricating a solid state circuit device having a transistor and an inductor comprising the steps of:

(a) introducing into one part of a doped semiconductor wafer an ingredient to form one region of said 5O transistor,

(b) introducing into another part of said doped semiconductor wafer an ingredient to form one region of said inductor,

(c) and applying to the Wafer electrically conductive means to connect said transistor and inductor in an electronic circuit, said method including the step of treating the wafer to provide electrical separation between the transistor and the inductor.

21. The method of fabricating a solid state circuit device having a transistor and a resistor comprising the steps of:

(a) introducing into one part of a doped semiconductor wafer an ingredient to form one region of said transistor,

(b) difiusing an ingredient into another part of said doped semiconductor wafer to form at least a part of said resistor,

(c) and applying electrical connecting means to the wafer to connect the transistor and the resistor in a circuit,

said method including the step of processing the wafer to provide electrical separation through the wafer between said parts of said wafer.

(References on following page) UNITED 1 1 1 2 References Cited by the Examiner 3,022,472 2/ 1962 Paskell.

STATES PATENTS 3,038,085 6/ 1962 Wallmark et a1.

l d WHITMORE A. WILTZ, Primary Examiner.

evernz. Pasken 5 F. Examlner. Johnson.

P. M. COHEN, Assistant Examiner. 

1. IN A METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT OF THE TYPE HAVING A PLURALITY OF SEPARATE TRANSISTORS AND A PLURALITY OF SEPARATE PASSIVE CIRCUIT COMPONENTS INCLUDING ELONGATED SEMICONDUCTOR RESISTOR IN A SEMICONDUCTOR BODY, THE STEPS OF DIFFUSING CONDUCTIVITY-DETERMINING IMPURITY MATERIAL INTO ONE FACE OF THE BODY TO CONVERT THE CONDUCTIVITY-TYPE OF SEMICONDUCTOR MATERIAL ADJACENT SAID ONE FACE TO FORM WHAT IN THE COMPLETED INTEGRATED CIRCUIT FUNCTIONS AS THE BASE REGIONS OF SAID PLURALITY OF TRANSISTORS AND TO FORM AT THE SAME TIME WHAT IN THE COMPLETED INTEGRATED CIRCUIT FUNCTIONS AS AT LEAST PARTS OF SAID PASCIVE CIRCUIT COMPONENTS, APPLYING CONTACTS TO A FACE OF THE BODY AT OPPOSITE ENDS OF SAID ELONGATED SEMICONDUCTOR RESISTORS, AND APPLYING INTERCONNECTIONS TO CONNECT SELECTED ONES OF THE PASSIVE CIRCUIT COMPONENTS INCLUDING SAID SEMICONDUCTOR RESISTORS OF SELECTED ONES OF THE TRANSSISTORS, THE METHOD INCLUDING THE STEPS OF TREATING THE BODY TO ELECTRICALLY ISOLATE SAID BASE REGIONS FROM ONE ANOTHER AND FROM SAID PARTS OF THE PASSIVE CIRCUIT COMPONENTS. 